RF Receiver: The Digital Receiver

RF Receiver · Digital Design

Taking the amplified signal to intermediate frequency, digitising it, and getting clean complex samples to the host.

Block diagram of the digital receiver chain — The digital receiver: down-conversion and decimation in a receiver chip, capture in one FPGA, routing to the host in a second.

A small FPGA module on a carrier board on the lab bench — The Artix-7 FPGA module of the receiver on its carrier board, at first connection on the bench (August 2026).

Three blue receiver evaluation boards labeled ADC3, ADC4 and ADC5 — Evaluation boards of the intermediate-frequency to baseband receiver chip, one per channel (October 2026).

The question

Once the signal is amplified, everything that follows is a question of sampling. A commercial spectrometer hides it. Ours exposes it: we choose the intermediate frequency, the decimation, and the point at which the data becomes complex baseband.

The architecture

An intermediate-frequency to baseband receiver chip performs the down-conversion and decimation, configured over a serial link from the FPGA.
One FPGA, on a low-cost Artix-7 development board, configures that chip and captures the triggered in-phase and quadrature sample stream.
A second FPGA multiplexes the sample packets of several channels onto a single serial link to the host.
Host-side tools in Python control the chain and recover the data.

Splitting capture from routing keeps the timing-critical path short.